
use crate::metadata::ir::*;
pub(crate) static REGISTERS: IR = IR {
    blocks: &[Block {
        name: "Syscfg",
        extends: None,
        description: Some("System configuration controller"),
        items: &[
            BlockItem {
                name: "memrmp",
                description: Some("memory remap register"),
                array: None,
                byte_offset: 0x0,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Memrmp"),
                }),
            },
            BlockItem {
                name: "cfgr1",
                description: Some("configuration register 1"),
                array: None,
                byte_offset: 0x4,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cfgr1"),
                }),
            },
            BlockItem {
                name: "exticr",
                description: Some("external interrupt configuration register 1"),
                array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
                byte_offset: 0x8,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Exticr"),
                }),
            },
            BlockItem {
                name: "scsr",
                description: Some("SCSR"),
                array: None,
                byte_offset: 0x18,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Scsr"),
                }),
            },
            BlockItem {
                name: "cfgr2",
                description: Some("CFGR2"),
                array: None,
                byte_offset: 0x1c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Cfgr2"),
                }),
            },
            BlockItem {
                name: "swpr",
                description: Some("SRAM2 write protection register"),
                array: None,
                byte_offset: 0x20,
                inner: BlockItemInner::Register(Register {
                    access: Access::Write,
                    bit_size: 32,
                    fieldset: Some("Swpr"),
                }),
            },
            BlockItem {
                name: "skr",
                description: Some("SKR"),
                array: None,
                byte_offset: 0x24,
                inner: BlockItemInner::Register(Register {
                    access: Access::Write,
                    bit_size: 32,
                    fieldset: Some("Skr"),
                }),
            },
            BlockItem {
                name: "swpr2",
                description: Some("SRAM2 write protection register 2"),
                array: None,
                byte_offset: 0x28,
                inner: BlockItemInner::Register(Register {
                    access: Access::Write,
                    bit_size: 32,
                    fieldset: Some("Swpr2"),
                }),
            },
            BlockItem {
                name: "imr1",
                description: Some("CPU1 interrupt mask register 1"),
                array: None,
                byte_offset: 0x100,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Imr1"),
                }),
            },
            BlockItem {
                name: "imr2",
                description: Some("CPU1 interrupt mask register 2"),
                array: None,
                byte_offset: 0x104,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Imr2"),
                }),
            },
            BlockItem {
                name: "c2imr1",
                description: Some("CPU2 interrupt mask register 1"),
                array: None,
                byte_offset: 0x108,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("C2imr1"),
                }),
            },
            BlockItem {
                name: "c2imr2",
                description: Some("CPU2 interrupt mask register 1"),
                array: None,
                byte_offset: 0x10c,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("C2imr2"),
                }),
            },
            BlockItem {
                name: "sipcr",
                description: Some("secure IP control register"),
                array: None,
                byte_offset: 0x110,
                inner: BlockItemInner::Register(Register {
                    access: Access::ReadWrite,
                    bit_size: 32,
                    fieldset: Some("Sipcr"),
                }),
            },
        ],
    }],
    fieldsets: &[
        FieldSet {
            name: "C2imr1",
            extends: None,
            description: Some("CPU2 interrupt mask register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "rtcstamp",
                    description: Some("Peripheral RTCSTAMP interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rtcwkup",
                    description: Some("Peripheral RTCWKUP interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rtcalarm",
                    description: Some("Peripheral RTCALARM interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rcc",
                    description: Some("Peripheral RCC interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "flash",
                    description: Some("Peripheral FLASH interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pka",
                    description: Some("Peripheral PKA interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "rng",
                    description: Some("Peripheral RNG interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "aes1",
                    description: Some("Peripheral AES1 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "comp",
                    description: Some("Peripheral COMP interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "adc",
                    description: Some("Peripheral ADC interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "C2imr2",
            extends: None,
            description: Some("CPU2 interrupt mask register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "dma1_ch1_im",
                    description: Some("Peripheral DMA1 CH1 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma1_ch2_im",
                    description: Some("Peripheral DMA1 CH2 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma1_ch3_im",
                    description: Some("Peripheral DMA1 CH3 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma1_ch4_im",
                    description: Some("Peripheral DMA1 CH4 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma1_ch5_im",
                    description: Some("Peripheral DMA1 CH5 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 4 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma1_ch6_im",
                    description: Some("Peripheral DMA1 CH6 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 5 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma1_ch7_im",
                    description: Some("Peripheral DMA1 CH7 interrupt mask to CPU2"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 6 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2_ch1_im",
                    description: Some("Peripheral DMA2 CH1 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2_ch2_im",
                    description: Some("Peripheral DMA2 CH2 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2_ch3_im",
                    description: Some("Peripheral DMA2 CH3 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 10 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2_ch4_im",
                    description: Some("Peripheral DMA2 CH4 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2_ch5_im",
                    description: Some("Peripheral DMA2 CH5 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 12 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2_ch6_im",
                    description: Some("Peripheral DMA2 CH6 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dma2_ch7_im",
                    description: Some("Peripheral DMA2 CH7 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "dmam_ux1_im",
                    description: Some("Peripheral DMAM UX1 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pvm1im",
                    description: Some("Peripheral PVM1IM interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pvm3im",
                    description: Some("Peripheral PVM3IM interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pvdim",
                    description: Some("Peripheral PVDIM interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tscim",
                    description: Some("Peripheral TSCIM interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "lcdim",
                    description: Some("Peripheral LCDIM interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cfgr1",
            extends: None,
            description: Some("configuration register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "boosten",
                    description: Some("I/O analog switch voltage booster enable"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c_pb6_fmp",
                    description: Some("Fast-mode Plus (Fm+) driving capability activation on PB6"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c_pb7_fmp",
                    description: Some("Fast-mode Plus (Fm+) driving capability activation on PB7"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 17 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c_pb8_fmp",
                    description: Some("Fast-mode Plus (Fm+) driving capability activation on PB8"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c_pb9_fmp",
                    description: Some("Fast-mode Plus (Fm+) driving capability activation on PB9"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 19 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c1_fmp",
                    description: Some("I2C1 Fast-mode Plus driving capability activation"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "i2c3_fmp",
                    description: Some("I2C3 Fast-mode Plus driving capability activation"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "fpu_ie",
                    description: Some("Floating Point Unit interrupts enable bits"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 6,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Cfgr2",
            extends: None,
            description: Some("CFGR2"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "cll",
                    description: Some("Cortex-M4 LOCKUP (Hardfault) output enable bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spl",
                    description: Some("SRAM2 parity lock bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pvdl",
                    description: Some("PVD lock enable bit"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "eccl",
                    description: Some("ECC Lock"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "spf",
                    description: Some("SRAM2 parity error flag"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 8 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Exticr",
            extends: None,
            description: Some("external interrupt configuration register 1"),
            bit_size: 32,
            fields: &[Field {
                name: "exti",
                description: Some("EXTI 0 configuration bits"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 3,
                array: Some(Array::Regular(RegularArray { len: 4, stride: 4 })),
                enumm: None,
            }],
        },
        FieldSet {
            name: "Imr1",
            extends: None,
            description: Some("CPU1 interrupt mask register 1"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "tim1im",
                    description: Some("Peripheral TIM1 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 13 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim16im",
                    description: Some("Peripheral TIM16 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 14 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "tim17im",
                    description: Some("Peripheral TIM17 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 15 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit5im",
                    description: Some("Peripheral EXIT5 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 21 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit6im",
                    description: Some("Peripheral EXIT6 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 22 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit7im",
                    description: Some("Peripheral EXIT7 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 23 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit8im",
                    description: Some("Peripheral EXIT8 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 24 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit9im",
                    description: Some("Peripheral EXIT9 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 25 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit10im",
                    description: Some("Peripheral EXIT10 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 26 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit11im",
                    description: Some("Peripheral EXIT11 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 27 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit12im",
                    description: Some("Peripheral EXIT12 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 28 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit13im",
                    description: Some("Peripheral EXIT13 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 29 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit14im",
                    description: Some("Peripheral EXIT14 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 30 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "exit15im",
                    description: Some("Peripheral EXIT15 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Imr2",
            extends: None,
            description: Some("CPU1 interrupt mask register 2"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "pvm1im",
                    description: Some("Peripheral PVM1 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 16 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pvm3im",
                    description: Some("Peripheral PVM3 interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 18 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "pvdim",
                    description: Some("Peripheral PVD interrupt mask to CPU1"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 20 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Memrmp",
            extends: None,
            description: Some("memory remap register"),
            bit_size: 32,
            fields: &[Field {
                name: "mem_mode",
                description: Some("Memory mapping selection"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 3,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Scsr",
            extends: None,
            description: Some("SCSR"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "sram2er",
                    description: Some("SRAM2 Erase"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "sram2bsy",
                    description: Some("SRAM2 busy by erase operation"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 1 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "c2rfd",
                    description: Some("CPU2 SRAM fetch (execution) disable."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 31 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Sipcr",
            extends: None,
            description: Some("secure IP control register"),
            bit_size: 32,
            fields: &[
                Field {
                    name: "saes",
                    description: Some("Enable AES1 KEY[7:0] security."),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                    bit_size: 1,
                    array: Some(Array::Regular(RegularArray { len: 2, stride: 1 })),
                    enumm: None,
                },
                Field {
                    name: "spka",
                    description: Some("Enable PKA security"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 2 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
                Field {
                    name: "srng",
                    description: Some("Enable True RNG security"),
                    bit_offset: BitOffset::Regular(RegularBitOffset { offset: 3 }),
                    bit_size: 1,
                    array: None,
                    enumm: None,
                },
            ],
        },
        FieldSet {
            name: "Skr",
            extends: None,
            description: Some("SKR"),
            bit_size: 32,
            fields: &[Field {
                name: "key",
                description: Some("SRAM2 write protection key for software erase"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 8,
                array: None,
                enumm: None,
            }],
        },
        FieldSet {
            name: "Swpr",
            extends: None,
            description: Some("SRAM2 write protection register"),
            bit_size: 32,
            fields: &[Field {
                name: "pwp",
                description: Some("P0WP"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 1,
                array: Some(Array::Regular(RegularArray { len: 32, stride: 1 })),
                enumm: None,
            }],
        },
        FieldSet {
            name: "Swpr2",
            extends: None,
            description: Some("SRAM2 write protection register 2"),
            bit_size: 32,
            fields: &[Field {
                name: "pwp",
                description: Some("P32WP"),
                bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
                bit_size: 1,
                array: Some(Array::Regular(RegularArray { len: 32, stride: 1 })),
                enumm: None,
            }],
        },
    ],
    enums: &[],
};
